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Technical Program Chairs Dr. Michael Fritze Prior to joining DARPA, Dr. Fritze was a staff member from 1995-2006 at MIT Lincoln Laboratory in Lexington, Massachusetts, a Federally-Funded Research and Development Center (FFRDC). At Lincoln Laboratory, he worked on fully-depleted silicon on insulator (FDSOI) technology development with an emphasis on novel devices. Particular interests included highly scaled, tunneling-based, and ultra-low power devices. Dr. Fritze also worked in the area of silicon-based integrated optics. Another research interest at Lincoln Laboratory was in the area of resolution-enhanced optical lithography and nanofabrication with particular emphasis on low volume technological solutions. Dr. Vivek Singh He is responsible for all of Intel's CAD and modeling tool development in full chip OPC, lithography verification, rigorous lithography modeling, next-generation lithography selection, inverse lithography technologies and double patterning. He also represents Intel on several external Design for Manufacturability (DFM) forums. Singh joined Intel in 1993 as a modeling applications engineer, was appointed team leader for the Resist and Applications Group in 1996, and was appointed overall leader of the Lithography Modeling Group in 2000.
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Dr. Michael Fritze has recently joined ISI. Prior to that Dr. Michael Fritze joined the DARPA Microsystems Technology Office (MTO) as a Program Manager in August 2006. His interests are in the areas of advanced low power electronics and low volume nanofabrication. Currently, Dr. Fritze is responsible for the 3D Integrated Circuits (3-D IC), Steep-Subthreshold-slope Transistors for Electronics with Extremely-Low Power (STEEP), Radiation Hardening by Design (RHBD), and Carbon Electronics for RF Applications (CERA) and Technology for Efficient Agile Mixed-Signal Microsystems (TEAM) Program for MTO.
Vivek Singh is an Intel Fellow and director of computational lithography in Intel's Technology and Manufacturing Group.